1. Field of the Invention
The present invention relates to a semiconductor device including a gate electrode and a pair of impurity diffusion regions (source/drain) and a manufacturing method of the same.
2. Description of the Related Art
Recently, further scale down and higher integration of a semiconductor device typified by a MOS transistor has been progressing. To respond to further scale down and higher integration, in the MOS transistor, as a technique for forming an element isolation structure, for example, the application of an STI method is proposed. Further, in this case, for example, as disclosed in Patent Document 1, a technique for reducing a resistance by forming a silicide layer on a source/drain in order to suppress an increase in the resistance value of the source/drain resulting from the application of the STI method is applied.
(Patent Document 1)
Japanese Patent Application Laid-open No. 2005-235255
To suppress an increase in junction leakage current by forming the silicide layer on the source/drain and fully reduce the resistance value of the source/drain, it is needed to form the silicide layer relatively thick if the realization of further scale down and higher integration of the MOS transistor is taken into account. However, the thicker the silicide layer is formed, the larger the erosion of the source/drain by a metal (for example, W, Ti, or the like) used for silicidation becomes, whereby it is difficult to form the silicide layer which is thick enough to reduce resistance.